1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device which reduces leakage current by controlling an etch of a field oxide layer when a contact hole is formed.
2. Discussion of Related Art
As the integration of a semiconductor device increases, so the size of an unit transistor decreases. Thus, sizes of contact holes exposing impurity regions are reduced as well as the impurity regions for source and drain regions are decreased in size, causing difficulty in process. Besides, leakage current on the operation of the device is brought about by the etch of a field oxide layer due to misalignment in forming the contact holes.
Therefore, a technique of forming a borderless contact has been developed to reduce leakage current by forming the contact hole to be overlapped with a field oxide layer, which provides an easy process and prevents the etch of the field oxide layer.
FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art.
Referring to FIG. 1A, a field oxide layer 13 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 11 by shallow trench isolation (hereinafter abbreviated STI). In this case, the field oxide layer 13 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 11, by forming trenches 12 which are slant to a predetermined degree by carrying out an anisotropic etch such as reaction ion etching(hereinafter abbreviated RIE) and the like on the exposed parts of the semiconductor substrate 11, by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.
After a gate oxide layer 15 has been formed on the active area of the semiconductor substrate 11, polysilicon doped with impurities is deposited on the gate insulating layer 15 by chemical vapor deposition(hereinafter abbreviated CVD). Then, a gate 17 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 11 by photolithography including anisotropic etches such as RME and the like.
Lightly doped regions 19 for LDD(lightly doped drain) regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 11 with n typed impurities in use of the gate 17 as a mask.
Referring to FIG. 1B, a sidewall spacer 21 is formed at the sides of the gate 17. In this case, the sidewall spacer 21 is formed by deposing silicon oxide on the semiconductor substrate 11 to cover the field oxide layer 13 and gate 17 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 11 exposed by RIE.
Heavily doped regions 23 for a source and a drain region are formed by implanting with n typed impurity ions heavily into the exposed portions of the semiconductor substrate 11 in use of the gate 17 and sidewall spacer 21 as a mask.
Referring to FIG. 1C, a first insulating interlayer  layer 25 is formed by depositing silicon nitride on the semiconductor substrate 11 by CVD to cover the field oxide layer 13, gate 17, and sidewall spacer  spacers 21 by CVD. And, a  A second insulating interlayer  layer 27 is formed by depositing silicon oxide or BPSG (boro phospho silicate glass) on the first insulating interlayer  layer 25 to a substantial thickness by CVD or by coating SOG (spin on glass) the first insulating interlayer  layer 25 with SOG(spin on glass) .
A first and a  First and second contact hole  holes 29 and 31 respectively exposing the gate 17 and heavily doped regions 23 respectively  are formed by patterning the second and first insulating interlayers  layers 27 and 25 by photolithography including anisotropic etch  etching such as RIE and the like. As the thickness of the second insulating interlayer  layer 27 is irregular due to the  a height difference between the gate 17 and heavily doped regions 23, the first and second contact holes 29 and 31 are formed by sufficiently etching, that is overetching the second insulating interlayer  layer 27 sufficiently, which means that the second insulating interlayer  layer 27 is overetched to expose portions of the first insulating interlayer  layer 25 corresponding  which correspond to the heavily doped regions 23, and then by etching the first insulating interlayer  layer 25.
In this case, as the  At this time, since an etch rate of the first insulating interlayer  layer 25 is different from that of the second insulating interlayer  layer 27, the first insulating interlayer  layer 25 serves as an etch stop layer and prevents the field oxide layer 13 from being etched in spite of  even when sufficiently etching the second insulating interlayer  layer 27sufficiently .
Referring to FIG. 1D, an electrically-conductive substance such as polysilicon, Al  aluminum, and the like is deposited on the second insulating interlayer  layer 27 and through the first and second contact holes 29 to 31 to be contacted  brought into contact with the gate 17 and heavily of  doped regions 23 through the first and second contact holes 29 and 31 . Then, a first and a  first and second plug  plugs 33 and 35 are formed in the first and second contact holes 29 and 31, respectively, by removing the electrically-conductive substance through chemical mechanical polishing (CMP) to expose the surface of the second insulating interlayer  layer 27by chemical-mechanical polishing(hereinafter abbreviated CMP) .
The  In the above-mentioned method of  for fabricating a semiconductor device prevents  according to the conventional art, in order to define the first and second contact holes which expose the gate and heavily doped regions, the second layer is over-etched to expose portions of the first insulating layer which correspond to the heavily doped regions, and then the first insulation layer dielectric is etched, whereby the field oxide layer is prevented from being etchedby overetching the second insulating interlayer to expose portions of the first insulating interlayer corresponding to the heavily doped regions for forming the first and second contact holes exposing the gate and heavily doped regions and by etching the first insulating interlayer successively .
Unfortunately  However, the method of  for fabricating a semiconductor device of the related art causes  suffers from defects in that a leakage current is likely to be generated due to the  a difference in heat expansion coefficient between the semiconductor substrate and the first insulating interlayer  layer made of silicon nitride as well as due to stress caused by lattice mismatch.